Modern system-on-chip (SoC) designs often have a substantial number of embedded memories on a single chip. These memories may be scattered around the device instead of being concentrated in one location. Typically, these memories are of different types and sizes. In addition, these memories may be further embedded inside embedded cores. This structure poses a challenge to testing all of the memories on the chips, as test access may be limited to only a few input/output (I/O) pins. Built-in self-test (BIST) logic is frequently used to test such embedded memories within SoCs, as BIST logic provides a simple and low-cost testing method with little to no performance impact. Specific testing may be required to test all of the memories on a device, which is known as memory built-in self-test (MBIST). As devices gain performance and functionality, the number of memories to support that performance and functionality grows, as does the need to test those memories. Like other BIST logic, MBIST logic may provide the capability to run one or more algorithms to verify memory functionality and to test for specific memory faults. As such, there is a general need to optimize MBIST algorithms to detect failures that may occur in a given memory device.